This invention relates generally to high-capacity data switches. In particular, it relates to a self-configuring distributed switch with a channel-switched core which automatically adapts to varying data traffic loads in a switched data network, and has a very high switching capacity.
The volume of data now exchanged through telecommunications networks requires data networks having a high data transfer capacity. Such networks must also serve large geographical areas. Network scalability to achieve a very high-capacity and wide-area coverage may be realized by increasing the number of nodes in a network and/or increasing the transfer capacity per node. For a given link capacity, e.g., 10 Gb/s, increasing the capacity per node necessitates increasing the number of links per node. In a balanced network, the mean number of hops per node pair is inversely proportional to the number of links per node. Decreasing the mean number of hops per node pair dramatically reduces network-control complexity, facilitates the routing function, and enables the realization of network-wide quality of service (QOS) objectives.
In order to decrease the number of hops per node pair in a network, very high-capacity switches are required. Consequently, methods are required for constructing very high-capacity switches. It is also desirable that such switches be distributed to permit switch access modules to be located in proximity of data traffic sources.
Advances in optical switching technology have greatly facilitated the construction of high-capacity switches using optical space switches in the switch core. The principal problem encountered in constructing high-capacity switches, however, is the complexity of coordinating the transfer of data between ingress and egress, while permitting the creation of new paths between the ingress and the egress. Consequently, there exists a need for a method of increasing data transfer capacity while simplifying data transfer control in a high-speed data switch.
The design of data switching systems has been extensively reported in the literature. Several design alternatives have been described. Switches of moderate capacity are preferably based on a common-buffer design. For higher capacity switches, the buffer-space-buffer switch and the linked-buffers switch have gained widespread acceptance. A switch based on an optical space-switched core is described in U.S. Pat. No. 5,475,679 which issued on Dec. 12, 1995 to Munter. An optical-core switching system is described in U.S. Pat. No. 5,575,320 which issued May 19, 1998 to Watanabe et al.
A buffer-space-buffer switch, also called a space-core switch, typically consists of a memoryless fabric connecting a number of ingress modules to a number of egress modules. The ingress and egress modules are usually physically paired, and an ingress/egress module pair often shares a common payload memory. An ingress/egress module pair that shares a common payload memory is hereafter referred to as an edge module. The passive memoryless fabric is preferably adapted to permit reconfiguration of the inlet-outlet paths within a predefined transient time. The memoryless core is completely unaware of the content of data streams that it switches. The core reconfiguration is effected by either a centralized or a distributed controller in response to spatial and temporal fluctuations in the traffic loads at the ingress modules.
The linked-buffers architecture includes module sets of electronic ingress modules, middle modules, and egress modules, and has been described extensively in the prior art. Each module is adapted to store data packets and forward the packets toward their respective destinations. The module-sets are connected in parallel using internal links of fixed capacity.
The control function for the linked-buffers switch is much simpler than the control function for the space-core switch. The capacity of the linked-buffers switch is limited by the capacity of each module-set, the number of internal links emanating from each ingress module, and the number of internal links terminating to each egress module. With a given module-set capacity, the capacity of a linked-buffers switch can be increased virtually indefinitely by increasing the number of internal links, which permits the number of module-sets in the switch to be accordingly increased. However, with a fixed module capacity, when the number of internal links is increased, the capacity of each internal link must be correspondingly reduced. Reducing the capacity of an internal link is not desirable because it limits the capacity that can be allocated to a given connection or a stream of connections. A switch with a space switch core does not suffer from this limitation.
The linked-buffers switch can be modified in a known way by replacing a module-set with a single module having a higher capacity than that of any of the modules in the module set. As described above, a module set includes an ingress module, a middle module, and an egress module. The modified configuration enables both direct and tandem connections between ingress and egress and is hereafter referred to as a mesh switch. The mesh switch enables direct switching from ingress to egress as well as tandem switching.
A disadvantage of the switching architectures described above is their limited scalability.
Prior art switches may be classified as channel switches that switch channels without examining the content of any channel, and content-aware data switches. A switched channel network has a coarse granularity. In switched data networks, inter-nodal links have fixed capacities. Consequently, fluctuations in traffic loads can require excessive tandem switching loads that can reduce the throughput and affect network performance.
There therefore exists a need for a self-configuring data switch that can adapt to fluctuations in data traffic loads.
It is therefore an object of the invention to provide a very high-capacity switch with a channel-switching core.
It is another object of the invention to provide an architecture for an expandable channel-switching core.
It is yet another object of the invention to provide a self-configuring switch that adjusts its internal module-pair capacity in response to fluctuations in data traffic volumes.
It is a further object of the invention to provide a data switch that implements both direct channel paths and tandem channel paths.
It is yet a further object of the invention to provide a data switch in which channel switching and connection routing are fully coordinated.
It is a further object of the invention to provide a method and an apparatus for time coordination of connection routing and path reconfiguration.
It is a further object of the invention to provide a method of interleaving time-critical data and delay-tolerant data on a shared transmission medium.
It is a further object of the invention to provide a method of assigning inter-module paths so as to maximize the use of direct ingress/egress data transfer.
The invention provides a self-configuring data switch comprising a number of electronic switch modules interconnected by a single-stage channel switch. The single-stage channel switch comprises a number P of parallel space switches each having n input ports and n output ports. Each of the electronic modules is preferably capable of switching variable-size packets and is connected to the set of P parallel space switches by W channels, Wxe2x89xa6P. A channel may be associated with a single wavelength in one of M multiple wavelength fiber links, where W/M is a positive integer. The maximum number of modules is the integer part of nxc3x97P/W. The capacity of each module may vary from a few gigabits per second (Gb/s) to a few terabits per second (Tb/s). The module capacity is shared between the core access links and the outer access links which are connected to data traffic sources and data traffic sinks, or other data switches.
The channel switch core permits any two modules to be connected by an integer number of channels. A channel has a predefined capacity, typically several Gb/s. In order to enable the switching of traffic streams at arbitrary transfer rates, the inter-module connection pattern is changed in response to fluctuations in data traffic load. However, it may not be possible to adaptively modify the paths between modules to accommodate all data traffic variations, and it may be uneconomical to establish under-utilized paths for node-pairs of low traffic. To overcome this difficulty, a portion of the data traffic flowing between a source module and a sink module may be switched through one or more intermediate modules. Thus, in effect, the switch functions as a hybrid of a channel switch and a linked-buffers data switch, benefiting from the elastic path capacity of the channel switch and the ease of control of the linked-buffers data switch.
Changes to the channel switch connectivity are preferably computed by a global controller which determines changes in the input-output configurations of some space switches. The reconfiguration may be implemented in each of the P space switches. To realize a smooth reconfiguration, it is preferable that the connectivity changes be implemented in one space switch at a time. The central controller ensures that one-to-one mapping, or one-to-many mapping, of the channels is preserved in order to avoid collision. A collision results from many-to-one mapping.
The switching modules need not be collocated with each other or with the space switch core. Consequently, the respective lengths of the links between the switching modules and the switch core may vary significantly. Hence, a timing mechanism is needed to coordinate the reconfiguration of the inter-module paths to ensure that data is not lost during reconfiguration. The timing mechanism is distributed. One of the modules is collocated with the channel switch core and hosts a global controller. The other switch modules may be located any desired distance from the channel switch core. Each of the modules operates a local cyclical time counter of a predetermined period. Each time the local counter turns zero, the module sends a timing packet to the global controller. On receipt of a timing packet, the global controller time-stamps the packet and places it in a transmit queue from which it is transferred back to its respective module. On receipt of the returned stamped timing packet, a module extracts the time-stamp information and uses it to adjust its time counter at an appropriate time. This coordinates the local time counter with the global time counter to enable switch reconfigurations with a minimal guard time. The guard time is also needed to compensate for transient periods in the channel switch during reconfiguration.